Vhdl言語で24進アップダウンカウンタってどう記述しますか？教えてください。

Vhdl言語で24進アップダウンカウンタってどう記述しますか？教えてください。

No.1 回答者： Georgia.Rain. 回答日時： 2023/01/04 12:21

これを24進に変更してみて下さい。

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

entity MC14510B is
port (
signal pe : in std_logic;
signal ci_not : inout std_logic;
signal reset : in std_logic;
signal updown : in std_logic;
signal clk : in std_logic;
signal p : in std_logic_vector (3 downto 0);
signal q : out std_logic_vector(3 downto 0);
signal co_not : inout std_logic
);
end;

architecture myarch of MC14510B is
begin

process(pe, ci_not, reset, updown, clk)
variable qtemp : std_logic_vector(3 downto 0);
variable cotemp : std_logic;
begin
if reset = '1' then
qtemp := "0000";
elsif clk'event and updown = '1' and ci_not = '1' then
if qtemp < 15 then
qtemp := qtemp + 1;
cotemp := '1';
else
qtemp := "0000";
cotemp := '0';
end if;
elsif clk'event and updown = '0' and ci_not = '1' then
if qtemp > 0 then
qtemp := qtemp - 1;
cotemp := '1';
else
qtemp := "0000";
cotemp := '0';
end if;
elsif ci_not = '0' then
qtemp := "1010";
cotemp := '1';
else
if pe = '1' then
p <= qtemp;
cotemp := '1';
else
qtemp := qtemp;
cotemp := '1';
end if;
end if;
q <= qtemp;
co_not <= cotemp;
end process;
end myarch;